| Name | Version | Summary | date |
| magia-flow |
0.2.0 |
Design flow integration and automation with Magia |
2024-05-11 21:01:26 |
| hdl-registers |
5.2.0 |
An open-source HDL register interface code generator fast enough to run in real time |
2024-05-07 11:54:42 |
| lctime |
0.0.24 |
CMOS standard-cell characterization kit. |
2024-04-15 19:48:00 |
| librecell |
0.0.23 |
DEPRECATED - use `lctime` and `lclayout` packages - CMOS layout generator and characterization. |
2024-04-14 20:31:06 |
| librecell-layout |
0.0.23 |
DEPRECATED - use `lclayout` package instead - CMOS standard-cell layout generator. |
2024-04-14 20:28:43 |
| librecell-lib |
0.0.23 |
DEPRECATED - use `lctime` - CMOS standard-cell characterization kit. |
2024-04-14 20:28:09 |
| peakrdl-regblock |
0.22.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-04-01 05:27:07 |